The present invention generally relates to a semiconductor memory circuit, and in particular to a semiconductor memory circuit such as a static random access memory and a dynamic random access memory. The present invention relates more particularly to a semiconductor memory circuit having a delay circuit which delays a write data signal and/or an address signal.
It is known that at the time of data write, a semiconductor memory circuit is provided with a write data signal, an address signal and a write enable signal from an external circuit such as a central processing unit (hereafter simply referred to as CPU). In a write cycle, there is defined a predetermined time relationship between the write data signal and the write enable signal which are generated by the CPU. That is, the predetermined relationship consists of a data setup time (T.sub.DW) and a data hold time (T.sub.DH). The data setup time defines a time duration between a time when the write data signal becomes valid and a time when the write enable signal disappears. The data hold time defines a time duration between a time when the write enable signal disappears and a time when the data signal becomes invalid. A sum (total time) of the data setup time and the data hold time corresponds to a data valid time.
A conventional semiconductor memory circuit includes a built-in delay circuit for delaying the write data signal applied to a data input terminal of the memory circuit in order to adjust timing of generation of the write data signal with respect to the write enable signal. For example, the Japanese Laid-Open Patent Application No. 203694/1983 discloses a memory circuit having a delay circuit of an inverter for delaying the write data signal by a fixed time t.sub.2. The disclosed delay circuit delays each of the beginning and end of the write data signal by the time t.sub.2. The delayed write data signal is supplied to a write amplifier built in the memory circuit.
Although the data setup time and the data hold time of the delayed write data signal are adjustable, the total time which is the sum thereof is always fixed. Therefore, when the data hold time is adjusted so as to be shortened, the data setup time is necessarily lengthened. Adversely when the data hold time is adjusted so as to be lengthened, the data setup time is necessarily shortened. That is, the conventional delay circuit cannot independently adjust timing of the beginning and end of the write data signal supplied from the CPU. Normally, both the data setup time and the data hold time which are determined by the CPU are required to be as short as possible in order to obtain a high-speed write operation. However, this requirement cannot be achieved by the above conventional memory circuit having the built-in delay circuit.